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| author |   Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 15:58:36 +0100 |
|---|---|---|
| committer |   Neil Armstrong <narmstrong@baylibre.com> | 2018-03-13 10:04:00 +0100 |
| commit | 7f9768a5405192d49c5d963f5e29c740315efca7 (patch) | |
| tree | 312cd704c8125e2f1ba422c33c0a884d309327b7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: meson: add regmap to the clock controllers (diff) | |
| download | wireguard-linux-7f9768a5405192d49c5d963f5e29c740315efca7.tar.xz wireguard-linux-7f9768a5405192d49c5d963f5e29c740315efca7.zip | |
clk: meson: migrate gates to clk_regmap
Move meson8b, gxbb and axg clocks using clk_gate to clk_regmap
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions