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author | 2016-12-20 08:54:29 -0700 | |
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committer | 2016-12-29 15:02:58 -0500 | |
commit | 88b333b0ed790f9433ff542b163bf972953b74d3 (patch) | |
tree | b3edf10c51b3faf7b36eda931236a257022185ba /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge tag 'drm-intel-next-fixes-2016-12-22' of git://anongit.freedesktop.org/git/drm-intel into drm-fixes (diff) | |
download | wireguard-linux-88b333b0ed790f9433ff542b163bf972953b74d3.tar.xz wireguard-linux-88b333b0ed790f9433ff542b163bf972953b74d3.zip |
drm/msm: Ensure that the hardware write pointer is valid
Currently the value written to CP_RB_WPTR is calculated on the fly as
(rb->next - rb->start). But as the code is designed rb->next is wrapped
before writing the commands so if a series of commands happened to
fit perfectly in the ringbuffer, rb->next would end up being equal to
rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR.
The easiest way to fix this is to mask WPTR when writing it to the
hardware; it makes the hardware happy and the rest of the ringbuffer
math appears to work and there isn't any point in upsetting anything.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
[squash in is_power_of_2() check]
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions