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| author |   Jianqun xu <jay.xu@rock-chips.com> | 2016-01-07 17:18:07 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2016-01-16 16:01:21 +0100 |
| commit | 8931f8e02979e4180566907019d432527c80abf7 (patch) | |
| tree | 0399de7b32777e4d928a4c940f1b125fe5a184c7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: rockchip: rk3036: rename emac ext source clock (diff) | |
| download | wireguard-linux-8931f8e02979e4180566907019d432527c80abf7.tar.xz wireguard-linux-8931f8e02979e4180566907019d432527c80abf7.zip | |
clk: rockchip: rk3368: fix some clock gates
Reference to the Rockchip RK3368 TRM v1.1, some clock
gates need to be updated.
Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions