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| author |   Guido Günther <agx@sigxcpu.org> | 2019-03-25 17:08:10 +0100 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2019-04-03 18:44:40 +0200 |
| commit | 8c089d642fd176dfab0dac9e0b71a16547de3d02 (patch) | |
| tree | c6775d34aa32391d88d8ec561eea08ac1afd5c03 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/panel: Add Feiyang FY07024DI26A30-D MIPI-DSI LCD panel (diff) | |
| download | wireguard-linux-8c089d642fd176dfab0dac9e0b71a16547de3d02.tar.xz wireguard-linux-8c089d642fd176dfab0dac9e0b71a16547de3d02.zip | |
dt-bindings: display/panel: Add missing unit names
Some examples were missing the unit names triggering
Warning (unit_address_vs_reg): .../panel: node has a reg or ranges property, but no unit name
warnings when used verbatim in DTs and running dtc with W=1.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/901e836ea06889a9d91a799102b2a6b836d93dcd.1553529797.git.agx@sigxcpu.org
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions