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| author |   Marc Zyngier <maz@kernel.org> | 2022-03-04 14:37:32 +0000 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-03-04 14:37:32 +0000 |
| commit | 8e6958c80ead0f9891c9db6f64841050f63785ba (patch) | |
| tree | 9b8aeb14167d1a4a7c7f8cc81cfbbcff17dacfcb /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branch irq/plic-cleanups into irq/irqchip-next (diff) | |
| parent | irqchip/xilinx: Switch to GENERIC_IRQ_MULTI_HANDLER (diff) | |
| download | wireguard-linux-8e6958c80ead0f9891c9db6f64841050f63785ba.tar.xz wireguard-linux-8e6958c80ead0f9891c9db6f64841050f63785ba.zip | |
Merge branch irq/misc-5.18 into irq/irqchip-next
* irq/misc-5.18:
: .
: Misc irq chip changes for 5.18
:
: - GICv3: Relax ordering of previous stores to only include the ISH domain
:
: - nvic: Unmap MMIo region on probe failure
:
: - xilinx: Switch to GENERIC_IRQ_MULTI_HANDLER when used on microblaze
: .
irqchip/xilinx: Switch to GENERIC_IRQ_MULTI_HANDLER
irqchip/nvic: Release nvic_base upon failure
irqchip/gic-v3: Use dsb(ishst) to order writes with ICC_SGI1R_EL1 accesses
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions