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| author |   Ryder Lee <ryder.lee@mediatek.com> | 2018-03-06 17:09:26 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2018-03-19 13:40:57 -0700 |
| commit | 936ceb12c5f72cd087149e3cf01347969a472801 (patch) | |
| tree | 25255cf397c5ceef3f7ad9765e7d73efd263d61d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: mediatek: fix PWM clock source by adding a fixed-factor clock (diff) | |
| download | wireguard-linux-936ceb12c5f72cd087149e3cf01347969a472801.tar.xz wireguard-linux-936ceb12c5f72cd087149e3cf01347969a472801.zip | |
clk: mediatek: update missing clock data for MT7622 audsys
Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions