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| author |   Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-01-27 22:38:34 +0100 |
|---|---|---|
| committer |   Ulf Hansson <ulf.hansson@linaro.org> | 2017-02-13 13:20:49 +0100 |
| commit | 9479074e93765a65ee352e74bb66ff3f5ec03413 (patch) | |
| tree | 55c14ca4d0b814da6cc6c67f79980a1b0b6ec368 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | mmc: sunxi: Fix clock frequency change sequence (diff) | |
| download | wireguard-linux-9479074e93765a65ee352e74bb66ff3f5ec03413.tar.xz wireguard-linux-9479074e93765a65ee352e74bb66ff3f5ec03413.zip | |
mmc: sunxi: Gate the clock when rate is 0
The MMC core assumes that the code will gate the clock when the bus
frequency is set to 0, which we've been ignoring so far.
Handle that.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions