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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-01-06 20:28:53 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-03 11:07:05 +0100 |
| commit | 989d673ff7c461b2abd472227fdb7df69860d23f (patch) | |
| tree | 55f2b5b52298184108c02f6b78c2b9d8c540cac6 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r9a08g045: Add clocks, resets and power domain support for the TSU IP (diff) | |
| download | wireguard-linux-989d673ff7c461b2abd472227fdb7df69860d23f.tar.xz wireguard-linux-989d673ff7c461b2abd472227fdb7df69860d23f.zip | |
clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI
Add clock and reset entries for the DRP-AI block, which is available only
on the Renesas RZ/V2L SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250106202853.262787-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions