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authorChristophe Leroy <christophe.leroy@c-s.fr>2017-07-12 12:08:51 +0200
committerMichael Ellerman <mpe@ellerman.id.au>2017-08-15 22:55:53 +1000
commita3059b0ca00bc3656ec47797e5816eeedaac3426 (patch)
tree9115e3dc598c95a3750fd9d699b5a38f873ea782 /tools/perf/scripts/python/export-to-postgresql.py
parentpowerpc/32: Avoid risk of unrecoverable TLBmiss inside entry_32.S (diff)
downloadwireguard-linux-a3059b0ca00bc3656ec47797e5816eeedaac3426.tar.xz
wireguard-linux-a3059b0ca00bc3656ec47797e5816eeedaac3426.zip
powerpc/8xx: Make pinning of ITLBs optional
As stated in a comment in head_8xx.S, today we "Always pin the first 8 MB ITLB to prevent ITLB misses while mucking around with SRR0/SRR1 in asm". This issue has just been cleared by the preceding patch, therefore we can make this pinning optional (on by default) and independent of DATA pinning. This patch also makes pinning of IMMR independent of pinning of DATA. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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