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authorDavid Heidelberg <david@ixit.cz>2021-12-12 00:38:17 +0100
committerHeiko Stuebner <heiko@sntech.de>2021-12-12 13:07:29 +0100
commita39891a6e420daeb55abc99cde4278511ac861d7 (patch)
treece25d0c218a3b8dc5f18ba08a70ef8e6a324a838 /tools/perf/scripts/python/export-to-postgresql.py
parentarm64: dts: rockchip: Add spi1 pins on Quartz64 A (diff)
downloadwireguard-linux-a39891a6e420daeb55abc99cde4278511ac861d7.tar.xz
wireguard-linux-a39891a6e420daeb55abc99cde4278511ac861d7.zip
arm64: dts: rockchip: Add missing secondary compatible for PX30 DSI
Add second DSI compatible to comply with DT schema validation comming in the second patch. Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20211211233818.88482-1-david@ixit.cz Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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