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| author |   Tony Lindgren <tony@atomide.com> | 2024-03-27 09:10:37 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2024-04-10 09:15:48 +0300 |
| commit | a65ae2810439472543f18cacf35d5c1241a05a22 (patch) | |
| tree | 874317952f442c325030d43d80f08fc576aa3be2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE (diff) | |
| download | wireguard-linux-a65ae2810439472543f18cacf35d5c1241a05a22.tar.xz wireguard-linux-a65ae2810439472543f18cacf35d5c1241a05a22.zip | |
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions