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| author |   Joshua Ashton <joshua@froggi.es> | 2021-09-15 00:59:47 +0100 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-09-23 15:17:29 -0400 |
| commit | a86396c3a742865821f29fdb3b9bb00e005d013f (patch) | |
| tree | a9c9f52c38d1a2d86de0c92e1b45051b8ac5e8e7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Use dcc_ind_blk value to set register directly (diff) | |
| download | wireguard-linux-a86396c3a742865821f29fdb3b9bb00e005d013f.tar.xz wireguard-linux-a86396c3a742865821f29fdb3b9bb00e005d013f.zip | |
drm/amd/display: Handle GFX10_RBPLUS modifiers for dcc_ind_blk
Adds the missing logic to set the correct value of dcc_ind_blk for this tiling version.
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions