diff options
| author |   Paul Burton <paul.burton@imgtec.com> | 2017-08-15 16:25:25 -0500 |
|---|---|---|
| committer |   Bjorn Helgaas <bhelgaas@google.com> | 2017-08-16 11:44:37 -0500 |
| commit | aac2e96bf9cce2bc61c13709d361875d2dbf098d (patch) | |
| tree | 013681a8f302d5d464b70f43e26f46d1e8c4d9b8 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | PCI: xilinx: Unify INTx & MSI interrupt decode (diff) | |
| download | wireguard-linux-aac2e96bf9cce2bc61c13709d361875d2dbf098d.tar.xz wireguard-linux-aac2e96bf9cce2bc61c13709d361875d2dbf098d.zip | |
PCI: xilinx: Don't enable config completion interrupts
The Xilinx AXI bridge for PCI Express device provides interrupts indicating
the completion of config space accesses. We have previously
enabled/unmasked them but do nothing with them besides acknowledge them.
Leave the interrupts masked in order to avoid servicing a large number of
pointless interrupts during boot.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Bharat Kumar Gogada <bharatku@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions