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| author |   Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-11-15 15:43:57 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-12-10 11:50:20 +0100 |
| commit | aaf7188d7f77bb8a6e043c70dc6cc6616c427762 (patch) | |
| tree | 7a6c8d41f12a1061f9661dc84664eb405580170e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: renesas: ulcb: Add sample Audio Codec settings (diff) | |
| download | wireguard-linux-aaf7188d7f77bb8a6e043c70dc6cc6616c427762.tar.xz wireguard-linux-aaf7188d7f77bb8a6e043c70dc6cc6616c427762.zip | |
arm64: dts: renesas: r9a08g045: Add the remaining SCIF interfaces
The Renesas RZ/G3S SoC has 6 SCIF interfaces. SCIF0 is used as debug
console. Add the remaining ones.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241115134401.3893008-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions