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| author |   Rafael Antognolli <rafael.antognolli@intel.com> | 2020-02-12 11:17:28 -0800 |
|---|---|---|
| committer |   Matt Roper <matthew.d.roper@intel.com> | 2020-02-18 10:04:32 -0800 |
| commit | ac204c1b34a2f0443265198a5e53795431794bd2 (patch) | |
| tree | e03bbe2d696adac4b8d176939e0452741b8cbb6b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/display: use intel_de_*() functions for register access (diff) | |
| download | wireguard-linux-ac204c1b34a2f0443265198a5e53795431794bd2.tar.xz wireguard-linux-ac204c1b34a2f0443265198a5e53795431794bd2.zip | |
drm/i915/tgl: Add Wa_1808121037 to tgl.
It's not clear whether this workaround is final yet, but the BSpec
indicates that userspace needs to set bit 9 of this register on demand:
"To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA"
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2501
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
[mattrope: Tweaked comment while applying]
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200212191728.25227-1-rafael.antognolli@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions