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| author |   Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> | 2015-02-19 10:42:55 -0500 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2015-02-25 16:16:47 +0900 |
| commit | b621f6d458e9d6315205d5667b9eb5592ef0433c (patch) | |
| tree | d12fe0341aecec4a3bea607bc27c54053683caa3 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: shmobile: r8a7791: tidyup SDHI register size on DTSI (diff) | |
| download | wireguard-linux-b621f6d458e9d6315205d5667b9eb5592ef0433c.tar.xz wireguard-linux-b621f6d458e9d6315205d5667b9eb5592ef0433c.zip | |
ARM: shmobile: r8a7790: Fix HSUSB clock to hp_clk from mp_clk
HSUSB uses hp_clk rather than mp_clk for H/W register access.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
[horms: updated changelog]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions