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| author |   Nicolas Pitre <nicolas.pitre@linaro.org> | 2015-01-15 23:41:54 +0100 |
|---|---|---|
| committer |   Russell King <rmk+kernel@arm.linux.org.uk> | 2015-01-16 14:49:08 +0000 |
| commit | c25630381c6e093819d86d9618798db932cc2d90 (patch) | |
| tree | 6091a27765e09308662ec19db31b653ecc2d4779 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: 8287/1: add bitrev.h file to support rbit instruction (diff) | |
| download | wireguard-linux-c25630381c6e093819d86d9618798db932cc2d90.tar.xz wireguard-linux-c25630381c6e093819d86d9618798db932cc2d90.zip | |
ARM: 8285/1: remove ARMv3 user access code again
This code was restored with commit 080fc66fb5 ("ARM: Bring back ARMv3 IO
and user access code") because the RiscPC memory bus does not understand
half-word load/stores. However only the IO code needed restoring since
the alternative user access code contains no half-word accesses, is
already used when CONFIG_PREEMPT is set and runs faster on a StrongARM.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions