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| author |   Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-02-13 11:14:58 +0200 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-03-19 09:31:48 +0200 |
| commit | c368dbe2de0a7fec2488eb7e4dcccfe25714ed2b (patch) | |
| tree | 413544b96925040497ea365ac49d694423538928 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: fix DPLL4 x2 clkouts on 3630 (diff) | |
| download | wireguard-linux-c368dbe2de0a7fec2488eb7e4dcccfe25714ed2b.tar.xz wireguard-linux-c368dbe2de0a7fec2488eb7e4dcccfe25714ed2b.zip | |
ARM: dts: use ti,fixed-factor-clock for dpll4_m4x2_mul_ck
We need to use set-rate-parent for dpll4_m4 clock path, so use the
ti,fixed-factor-clock version which supports set-rate-parent property.
The set-rate-parent flag itself is set in the following patch, this one
just changes the clock driver to ti,fixed-factor-clock without any other
changes.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: Christoph Fritz <chf.fritz@googlemail.com>
Tested-by: Marek Belisko <marek@goldelico.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions