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| author |   Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2019-12-08 19:05:24 +0100 |
|---|---|---|
| committer |   Kevin Hilman <khilman@baylibre.com> | 2019-12-11 11:26:26 -0800 |
| commit | c4ac5c37a4a5c5ce94f70542d006568bd4b7d685 (patch) | |
| tree | 7c8a374fdae23bc50063b4243bed9b3ed6a07b12 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: meson: provide the XTAL clock using a fixed-clock (diff) | |
| download | wireguard-linux-c4ac5c37a4a5c5ce94f70542d006568bd4b7d685.tar.xz wireguard-linux-c4ac5c37a4a5c5ce94f70542d006568bd4b7d685.zip | |
ARM: dts: meson8: add the DDR clock controller
Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions