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| author |   Matt Roper <matthew.d.roper@intel.com> | 2020-07-16 15:05:47 -0700 |
|---|---|---|
| committer |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2020-08-17 16:15:58 -0400 |
| commit | cd803bb4f8a8d7b2c27c464ae32af14005cce7a1 (patch) | |
| tree | 9e7c95d72d1689c35f11d8c9c903e59af56243c8 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915: Move WaDisableDopClockGating:skl to skl_init_clock_gating() (diff) | |
| download | wireguard-linux-cd803bb4f8a8d7b2c27c464ae32af14005cce7a1.tar.xz wireguard-linux-cd803bb4f8a8d7b2c27c464ae32af14005cce7a1.zip | |
drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.
v2:
- Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
- Checkpatch style fixes
Bspec: 50287
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200716220551.2730644-2-matthew.d.roper@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions