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| author |   tianshuliang <tianshuliang@hisilicon.com> | 2018-03-05 15:01:32 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2018-03-12 15:56:58 +0800 |
| commit | d1b0399543cec5fa5d3a2d33b525a7cd7912e635 (patch) | |
| tree | f74b85562993665f1ca88758acdd8f52f7ee5fe6 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: hisilicon: add hisi phase clock support (diff) | |
| download | wireguard-linux-d1b0399543cec5fa5d3a2d33b525a7cd7912e635.tar.xz wireguard-linux-d1b0399543cec5fa5d3a2d33b525a7cd7912e635.zip | |
clk: hi3798cv200: add emmc sample and drive clock
It adds eMMC sample clock HISTB_MMC_SAMPLE_CLK and drive clock
HISTB_MMC_DRV_CLK support for Hi3798cv200 SoC.
Signed-off-by: tianshuliang <tianshuliang@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions