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| author |   Icenowy Zheng <icenowy@aosc.io> | 2019-07-28 11:12:26 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@bootlin.com> | 2019-08-23 09:14:48 +0200 |
| commit | d400cc4ad18f55a8253b2694f5594738e5cfacc2 (patch) | |
| tree | 2ea1113676fe8668a5411dc0639242a189b7f7ec /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: allwinner: orange-pi-3: Enable HDMI output (diff) | |
| download | wireguard-linux-d400cc4ad18f55a8253b2694f5594738e5cfacc2.tar.xz wireguard-linux-d400cc4ad18f55a8253b2694f5594738e5cfacc2.zip | |
dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board
The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash.
It has a gold finger connector for expansion, and UART is available from
reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or
Allwinner V3L SoCs.
Add the device tree binding of the basic version of the core board --
w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions