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| author |   Sam Protsenko <semen.protsenko@linaro.org> | 2021-12-14 19:09:24 +0200 |
|---|---|---|
| committer |   Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2021-12-15 08:34:47 +0100 |
| commit | d56a8e9c7af835a4f3f88b2ae34f4ba6f7085b7c (patch) | |
| tree | b88c9111c570c6fe1757ec3a43cb43e37ba3ed87 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: exynos: convert serial_0 to USI on ExynosAutov9 (diff) | |
| download | wireguard-linux-d56a8e9c7af835a4f3f88b2ae34f4ba6f7085b7c.tar.xz wireguard-linux-d56a8e9c7af835a4f3f88b2ae34f4ba6f7085b7c.zip | |
dt-bindings: soc: samsung: Fix I2C clocks order in USI binding example
Now that HSI2C binding [1] is converted to dt-schema format, it reveals
incorrect HSI2C clocks order in USI binding example:
.../exynos-usi.example.dt.yaml:
i2c@13820000: clock-names:0: 'hsi2c' was expected
From schema: .../i2c-exynos5.yaml
.../exynos-usi.example.dt.yaml:
i2c@13820000: clock-names:1: 'hsi2c_pclk' was expected
From schema: .../i2c-exynos5.yaml
Change HSI2C clock order in USI binding example to satisfy HSI2C binding
requirements and fix above warnings.
[1] Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20211214170924.27998-1-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions