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author | 2020-07-08 12:45:00 +0800 | |
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committer | 2020-07-21 15:37:38 -0400 | |
commit | d8e0b16d818ebd76386029fe098cddbae49bfaf5 (patch) | |
tree | 184b5f5203359afbbffeac4ff0c309ffa0015493 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | drm/amd/powerplay: revise the calling flow on OD table update (diff) | |
download | wireguard-linux-d8e0b16d818ebd76386029fe098cddbae49bfaf5.tar.xz wireguard-linux-d8e0b16d818ebd76386029fe098cddbae49bfaf5.zip |
drm/amd/powerplay: tag swSMU code layers
Per designs, the swSMU code is separated into four layers. And the typical
calling flow should be like: amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c
-> smu_cmn.c. Compile errors will come out for any violations. This can
help to prevent cross callings(e.g. amdgpu_smu.c -> ${asic}_ppt.c ->
amdgpu_smu.c -> ${asic}_ppt.c) which were common in our code.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions