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| author |   Swapnil Jakhade <sjakhade@cadence.com> | 2021-12-23 07:01:33 +0100 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2021-12-27 16:35:09 +0530 |
| commit | da08aab940092a050a4fb2857ed9479d2b0e03c4 (patch) | |
| tree | e3316629dfc80c3b8219ede73d9ffdcf85206a17 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | phy: cadence: Sierra: Update single link PCIe register configuration (diff) | |
| download | wireguard-linux-da08aab940092a050a4fb2857ed9479d2b0e03c4.tar.xz wireguard-linux-da08aab940092a050a4fb2857ed9479d2b0e03c4.zip | |
phy: cadence: Sierra: Fix to get correct parent for mux clocks
Fix get_parent() callback to return the correct index of the parent for
PLL_CMNLC1 clock. Add a separate table of register values corresponding
to the parent index for PLL_CMNLC1. Update set_parent() callback
accordingly.
Fixes: 28081b72859f ("phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)")
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-12-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions