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| author |   Michal Simek <michal.simek@amd.com> | 2024-12-11 13:41:32 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2025-02-03 17:05:50 +0100 |
| commit | dd6c921af2d3e2de1c49488432504d7f4f783bea (patch) | |
| tree | e308234a1ace543e3bf8291e0a70b0198f079211 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: zynq: Fix fpga region DT nodes name (diff) | |
| download | wireguard-linux-dd6c921af2d3e2de1c49488432504d7f4f783bea.tar.xz wireguard-linux-dd6c921af2d3e2de1c49488432504d7f4f783bea.zip | |
ARM: zynq: Enable QSPIs on platforms
Enable QSPIs with default MTD layout used for testing.
Zybos, Microzed and Zturn are only enabling controller without specifying
MTD map.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b10d922fec7fde0948205b266bf7e960113859c5.1733920873.git.michal.simek@amd.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions