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| author |   Jisheng Zhang <jszhang@kernel.org> | 2021-03-30 02:09:11 +0800 |
|---|---|---|
| committer |   Marc Zyngier <maz@kernel.org> | 2021-04-07 13:25:52 +0100 |
| commit | e03b7c1bcbfad6f27b4682f638b98627c4e416ba (patch) | |
| tree | fdfa051db457610f2bca000fc3827d2a4dc63c79 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | irqchip/hisi: Use the correct HiSilicon copyright (diff) | |
| download | wireguard-linux-e03b7c1bcbfad6f27b4682f638b98627c4e416ba.tar.xz wireguard-linux-e03b7c1bcbfad6f27b4682f638b98627c4e416ba.zip | |
irqchip/sifive-plic: Mark two global variables __ro_after_init
All of these two are never modified after init, so they can be
__ro_after_init.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210330020911.26423e9e@xhacker
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions