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| author |   Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> | 2018-02-23 14:15:18 -0800 |
|---|---|---|
| committer |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-02-27 12:06:26 -0800 |
| commit | e2770e2e0509e8b1189e2471af3012d68ca511a2 (patch) | |
| tree | fb124596e0a584cfab054e53da7038ee3545a862 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/psr: Extract PSR DPCD initialization and move it to intel_psr.c (diff) | |
| download | wireguard-linux-e2770e2e0509e8b1189e2471af3012d68ca511a2.tar.xz wireguard-linux-e2770e2e0509e8b1189e2471af3012d68ca511a2.zip | |
drm/i915/psr: Check for the specific AUX_FRAME_SYNC cap bit.
The cap check should be specifically for bit 0 instead of any bit.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Fixes: 474d1ec4a3d7 ("drm/i915/skl: Enabling PSR2 SU with frame sync")
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180223221520.18464-4-dhinakaran.pandiyan@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions