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| author |   Arnd Bergmann <arnd@arndb.de> | 2023-10-16 23:14:09 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2023-10-16 23:14:10 +0200 |
| commit | e4078ebbddf69f5a82f164dc07d50321b7f641cf (patch) | |
| tree | fc8c0d24dd990f3462e6b659d5eb9c081468ab70 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge tag 'qcom-arm64-fixes-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes (diff) | |
| parent | riscv: dts: starfive: visionfive 2: correct spi's ss pin (diff) | |
| download | wireguard-linux-e4078ebbddf69f5a82f164dc07d50321b7f641cf.tar.xz wireguard-linux-e4078ebbddf69f5a82f164dc07d50321b7f641cf.zip | |
Merge tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes
RISC-V Devicetrees for v6.6-final
A single fix for the Starfive VisionFive 2 platform so that chip select
for SPI matches the vendor documentation.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: starfive: visionfive 2: correct spi's ss pin
Link: https://lore.kernel.org/r/20231015-outmatch-tragedy-228f91d396b5@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions