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author | 2020-05-08 11:59:18 +0200 | |
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committer | 2020-05-11 10:31:24 +0200 | |
commit | e47cb97f153193d4b41ca8d48127da14513d54c7 (patch) | |
tree | b800cc520340c15f90dab6801613bc9812c1f0c1 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | ARM: dts: r7s9210: Remove bogus clock-names from OSTM nodes (diff) | |
download | wireguard-linux-e47cb97f153193d4b41ca8d48127da14513d54c7.tar.xz wireguard-linux-e47cb97f153193d4b41ca8d48127da14513d54c7.zip |
ARM: dts: r8a7740: Add missing extal2 to CPG node
The Clock Pulse Generator (CPG) device node lacks the extal2 clock.
This may lead to a failure registering the "r" clock, or to a wrong
parent for the "usb24s" clock, depending on MD_CK2 pin configuration and
boot loader CPG_USBCKCR register configuration.
This went unnoticed, as this does not affect the single upstream board
configuration, which relies on the first clock input only.
Fixes: d9ffd583bf345e2e ("ARM: shmobile: r8a7740: add SoC clocks to DTS")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200508095918.6061-1-geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions