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| author |   Lucas Stach <l.stach@pengutronix.de> | 2019-11-18 16:12:06 +0100 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2019-11-18 16:11:47 +0000 |
| commit | e48fdb53bd1fa50796b5a050e6e31fde3891a2c8 (patch) | |
| tree | 18f52d2f93a59ae7db5ac80a42ad9161f8482955 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: SOF: Intel: Fix CFL and CML FW nocodec binary names. (diff) | |
| download | wireguard-linux-e48fdb53bd1fa50796b5a050e6e31fde3891a2c8.tar.xz wireguard-linux-e48fdb53bd1fa50796b5a050e6e31fde3891a2c8.zip | |
ASoC: tlv320aic31xx: configure output common-mode voltage
The tlv320aic31xx devices allow to adjust the output common-mode voltage
for best analog performance. The datasheet states that the common mode
voltage should be set to be <= AVDD/2.
This changes allows to configure the output common-mode voltage via a DT
property. If the property is absent the voltage is automatically chosen
as the highest voltage below/equal to AVDD/2.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.kernel.org/r/20191118151207.28576-1-l.stach@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions