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| author |   Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-11-23 20:53:07 +0100 |
|---|---|---|
| committer |   Kevin Hilman <khilman@baylibre.com> | 2018-12-04 16:48:12 -0800 |
| commit | e8c276d953d800adced2c6174310320f90c5d432 (patch) | |
| tree | 3e00edc3afcfb5ed816ed5b5d85296f8e834ea1c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge tag 'meson-clk-headers-4.21-1' of git://github.com/BayLibre/clk-meson into v4.21/dt (diff) | |
| download | wireguard-linux-e8c276d953d800adced2c6174310320f90c5d432.tar.xz wireguard-linux-e8c276d953d800adced2c6174310320f90c5d432.zip | |
ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripherals
The public Meson8b (S805) datasheet describes a memory region called "A9
Periph base" which starts at 0xC4300000 and ends at 0xC430FFFF. Add a
simple-bus node and move all peripherals that are part of this memory
region.
This makes the .dts a bit easier to read. No functional changes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions