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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2021-06-26 09:13:36 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-12 10:52:03 +0200 |
| commit | e93c1373613fb2f3e59db5f13271f155820e6a67 (patch) | |
| tree | 6df1fe2ec8d5791752fc131854917496fec37613 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: rzg2l: Add multi clock PM support (diff) | |
| download | wireguard-linux-e93c1373613fb2f3e59db5f13271f155820e6a67.tar.xz wireguard-linux-e93c1373613fb2f3e59db5f13271f155820e6a67.zip | |
clk: renesas: r9a07g044: Rename divider table
As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV
and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename
clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it
can be reused.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions