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| author |   Sebastian Ott <sebott@linux.ibm.com> | 2018-09-27 13:57:12 +0200 |
|---|---|---|
| committer |   Martin Schwidefsky <schwidefsky@de.ibm.com> | 2019-04-29 10:47:01 +0200 |
| commit | e979ce7bced2ee019b5b1a040295484bd7f23680 (patch) | |
| tree | c2c7b88423ea2011ab2bab5fa05f5c393d5b9493 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | s390/airq: provide cacheline aligned ivs (diff) | |
| download | wireguard-linux-e979ce7bced2ee019b5b1a040295484bd7f23680.tar.xz wireguard-linux-e979ce7bced2ee019b5b1a040295484bd7f23680.zip | |
s390/pci: provide support for CPU directed interrupts
Up until now all interrupts on s390 have been floating. For MSI interrupts
we've used a global summary bit vector (with a bit for each function) and
a per-function interrupt bit vector (with a bit per MSI).
This patch introduces a new IRQ delivery mode: CPU directed interrupts.
In this new mode a per-CPU interrupt bit vector is used (with a bit per
MSI per function). Further it is now possible to direct an IRQ to a
specific CPU so we can finally support IRQ affinity.
If an interrupt can't be delivered because the appointed CPU is occupied
by a hypervisor the interrupt is delivered floating. For this a global
summary bit vector is used (with a bit per CPU).
Signed-off-by: Sebastian Ott <sebott@linux.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions