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| author |   Sung Lee <sung.lee@amd.com> | 2020-04-20 11:38:30 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-05-05 13:10:52 -0400 |
| commit | e9a135a969352e5cc945a8db636163a7bb8e4ada (patch) | |
| tree | 0d78d4e8e33a352677502eea8b769b037dc3c647 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Move panel_cntl specific register from abm to panel_cntl. (diff) | |
| download | wireguard-linux-e9a135a969352e5cc945a8db636163a7bb8e4ada.tar.xz wireguard-linux-e9a135a969352e5cc945a8db636163a7bb8e4ada.zip | |
drm/amd/display: Update DCN2.1 DV Code Revision
[WHY & HOW]
There is a problem in hscale_pixel_rate, the bug
causes DCN to be more optimistic (more likely to underflow)
in upscale cases during prefetch.
This commit ports the fix from DV code to address these issues.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions