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| author |   Dmitry Osipenko <digetx@gmail.com> | 2018-01-10 16:59:43 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2018-03-12 13:59:05 +0100 |
| commit | ea141d5819db989eb688cee2713b664faba4f1ca (patch) | |
| tree | a36e14e7a9f6834d33a7e8f97bd9aa756aa10457 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: tegra: Mark HCLK, SCLK and EMC as critical (diff) | |
| download | wireguard-linux-ea141d5819db989eb688cee2713b664faba4f1ca.tar.xz wireguard-linux-ea141d5819db989eb688cee2713b664faba4f1ca.zip | |
clk: tegra20: Correct PLL_C_OUT1 setup
PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's
set it to 240 MHz and explicitly specify HCLK rate for consistency.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions