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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2021-11-23 14:14:19 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-26 14:08:20 +0100 |
| commit | eb7621ce3362639025e7db125559e235a76d814f (patch) | |
| tree | 9b7181aa2dd5101c21eb280661b77ad9ec2cbd63 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: renesas: r9a07g044: Rename SDHI clocks (diff) | |
| download | wireguard-linux-eb7621ce3362639025e7db125559e235a76d814f.tar.xz wireguard-linux-eb7621ce3362639025e7db125559e235a76d814f.zip | |
arm64: dts: renesas: r9a07g044: Add WDT nodes
Add WDT{0, 1, 2} nodes to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211123141420.23529-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions