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author | 2020-12-07 13:26:51 -0800 | |
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committer | 2020-12-07 13:26:51 -0800 | |
commit | f4ac0c5639b75ef25071affe746b1e70d6d23e09 (patch) | |
tree | 71f87572455d6a03055b6a92a95d630f6c37d4f9 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Linux 5.10-rc1 (diff) | |
parent | clk: rockchip: fix i2s gate bits on rk3066 and rk3188 (diff) | |
download | wireguard-linux-f4ac0c5639b75ef25071affe746b1e70d6d23e09.tar.xz wireguard-linux-f4ac0c5639b75ef25071affe746b1e70d6d23e09.zip |
Merge tag 'v5.11-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
Added arch-dependencies for the newly added per-soc config symbols,
an unneeded redundancy removed and making i2s actually work on the
rk3066.
* tag 'v5.11-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix i2s gate bits on rk3066 and rk3188
clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks
clk: rockchip: Remove redundant null check before clk_prepare_enable
clk: rockchip: Add appropriate arch dependencies
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions