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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2015-10-16 11:41:19 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-12-08 14:33:02 +0100 |
| commit | f793d1e51705b276f083c1dc0dc75fb4cc4375c7 (patch) | |
| tree | 9489dbd16a5ad04e63cf40b3ec5bb97a640a6f99 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: shmobile: div6: Extract cpg_div6_register() (diff) | |
| download | wireguard-linux-f793d1e51705b276f083c1dc0dc75fb4cc4375c7.tar.xz wireguard-linux-f793d1e51705b276f083c1dc0dc75fb4cc4375c7.zip | |
clk: shmobile: Add new CPG/MSSR driver core
Add the common core for the new Renesas Clock Pulse Generator / Module
Standby and Software Reset driver.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions