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author | 2015-10-18 00:35:55 +0300 | |
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committer | 2015-11-18 18:01:19 +0200 | |
commit | f83ee67fcf8d743e7fbcb08c70fcd32c253bb2fa (patch) | |
tree | d9dd4801f0f2505b42f621030d57ce1287813aa5 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | arm: dts: ea3250/phy3250: specify phys memory offset for lpc32xx boards (diff) | |
download | wireguard-linux-f83ee67fcf8d743e7fbcb08c70fcd32c253bb2fa.tar.xz wireguard-linux-f83ee67fcf8d743e7fbcb08c70fcd32c253bb2fa.zip |
arm: dts: lpc32xx: add external memory controller device node
The change adds a description of ARM PrimeCell PL175 memory
controller, which is found on NXP LPC32xx SoCs.
The controller supports up to 4 static memory devices mapped to
0xE000 0000 - 0xE3FF FFFF physical memory area.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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