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| author |   Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2020-09-09 22:13:28 +0900 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2020-09-10 16:58:13 +0200 |
| commit | fa2d185f7518423ffcdba617ad09ff77ac51f198 (patch) | |
| tree | 46996de71e38acfd680f67a9b4fb507a9c1b1e19 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: power: Add r8a779a0 SYSC power domain definitions (diff) | |
| download | wireguard-linux-fa2d185f7518423ffcdba617ad09ff77ac51f198.tar.xz wireguard-linux-fa2d185f7518423ffcdba617ad09ff77ac51f198.zip | |
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V3U (R8A779A0) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1599657211-17504-2-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions