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| author | 2017-08-19 14:48:35 +0200 | |
|---|---|---|
| committer | 2017-08-21 17:15:59 +0100 | |
| commit | 5f93b0639634929b8349f9f9d83e1d881c1c7d4a (patch) | |
| tree | c20b83a4bd85b14ae2abb4a3c9d8212cd979162b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: sun4i-i2s: bclk and lrclk polarity tidyup (diff) | |
| download | wireguard-linux-5f93b0639634929b8349f9f9d83e1d881c1c7d4a.tar.xz wireguard-linux-5f93b0639634929b8349f9f9d83e1d881c1c7d4a.zip | |
ASoC: sun4i-i2s: Add mclk enable regmap field
The location of the mclk output enable bit is different on newer
SoCs. Use a regmap field to enable it.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions
