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| author |   Jeeja KP <jeeja.kp@intel.com> | 2016-06-03 18:29:35 +0530 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2016-06-07 14:19:11 +0100 |
| commit | 353f72aa77581926c0634fffe168f206435a8fc6 (patch) | |
| tree | e7c48ef6b5972203f55cd6aee18cbe2857d4b164 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: Intel: Skylake: Reset DSP pipe when host/link DMA is reset (diff) | |
| download | wireguard-linux-353f72aa77581926c0634fffe168f206435a8fc6.tar.xz wireguard-linux-353f72aa77581926c0634fffe168f206435a8fc6.zip | |
ASoC: Intel: Skylake: Set the pipe state to paused when paused
When pipe is stopped/Paused, set the pipe state to paused instead
of created.
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions