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| author |   Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-11-10 20:15:57 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-19 10:45:24 +0100 |
| commit | 52e844ee9a6f460e6160736a43ef13317a91ca74 (patch) | |
| tree | 4ba6df536f38b77dd9dad55f88a669090dd8b0a9 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes (diff) | |
| download | wireguard-linux-52e844ee9a6f460e6160736a43ef13317a91ca74.tar.xz wireguard-linux-52e844ee9a6f460e6160736a43ef13317a91ca74.zip | |
arm64: dts: reneas: rzg2: Add SDnH clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-9-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-10-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-11-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-12-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions