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| author |   Chunfeng Yun <chunfeng.yun@mediatek.com> | 2017-03-31 15:35:31 +0800 |
|---|---|---|
| committer |   Kishon Vijay Abraham I <kishon@ti.com> | 2017-04-10 16:43:40 +0530 |
| commit | 8d6e1957f14dbfb4c9510cd8179e3c8c1f488433 (patch) | |
| tree | 1e3e4fa92278dd14683804b8592da49f9b581772 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | phy: phy-mt65xx-usb3: move clock from phy node into port nodes (diff) | |
| download | wireguard-linux-8d6e1957f14dbfb4c9510cd8179e3c8c1f488433.tar.xz wireguard-linux-8d6e1957f14dbfb4c9510cd8179e3c8c1f488433.zip | |
phy: phy-mt65xx-usb3: add support for new version phy
There are some variations from mt2701 to mt2712:
1. banks shared by multiple ports are put back into each port,
such as SPLLC and U2FREQ;
2. add a new bank MISC for u2port, and CHIP for u3port;
3. bank's offset in each port are also rearranged;
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions