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| author |   Hao Chen <chenhao418@huawei.com> | 2023-10-24 11:20:34 +0800 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2023-10-25 09:23:16 +0100 |
| commit | 8ee2843f4d52026ab67e7577eaa49d444e1976b8 (patch) | |
| tree | 34686a4d744fa90779f4e35d6e7270dc9e31bf78 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branch 'dsa-microchip-WoL-support' (diff) | |
| download | wireguard-linux-8ee2843f4d52026ab67e7577eaa49d444e1976b8.tar.xz wireguard-linux-8ee2843f4d52026ab67e7577eaa49d444e1976b8.zip | |
net: hns3: add some link modes for hisilicon device
Add HCLGE_SUPPORT_50G_R1_BIT and HCLGE_SUPPORT_100G_R2_BIT two
capability bits and Corresponding link modes.
Signed-off-by: Hao Chen <chenhao418@huawei.com>
Signed-off-by: Jijie Shao <shaojijie@huawei.com>
Reviewed-by: Wojciech Drewek <wojciech.drewek@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions