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| author |   Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2024-06-21 16:11:28 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2024-08-27 17:53:51 -0400 |
| commit | 9793a4a6e5eb8764c7410c361984ed01722bab9f (patch) | |
| tree | 9fceadd214233770ae99f111d35c0cbfa9f3088a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Fix Synaptics Cascaded Panamera DSC Determination (diff) | |
| download | wireguard-linux-9793a4a6e5eb8764c7410c361984ed01722bab9f.tar.xz wireguard-linux-9793a4a6e5eb8764c7410c361984ed01722bab9f.zip | |
drm/amd/display: Notify DMCUB of D0/D3 state
[Why]
We want to avoid arming the HPD timer in firmware when preparing for
S0i3 entry when DC is considered in D3.
[How]
Notify DMCUB of the power state transitions so it can decide to arm
the HPD timer for idle in DCN35 only in D0.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ovidiu Bunea <Ovidiu.Bunea@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions