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| author |   Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-11-10 20:16:01 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-19 10:51:47 +0100 |
| commit | eca6ab6e362e3ae22b6c2769c4b6911bd0fb8ab1 (patch) | |
| tree | a701c2aa92491d9410e268c365697616e9013b76 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: reneas: rzg2: Add SDnH clocks (diff) | |
| download | wireguard-linux-eca6ab6e362e3ae22b6c2769c4b6911bd0fb8ab1.tar.xz wireguard-linux-eca6ab6e362e3ae22b6c2769c4b6911bd0fb8ab1.zip | |
arm64: dts: reneas: rcar-gen3: Add SDnH clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-13-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-14-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-15-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-16-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-17-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-18-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-19-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-22-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions