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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-11-09 12:31:10 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-15 10:06:13 +0100 |
| commit | f9a2adcc9e908907129c18518d4ea6195c44bf00 (patch) | |
| tree | 26f77c965e495204ddcf64ef363ba43469212d6e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board (diff) | |
| download | wireguard-linux-f9a2adcc9e908907129c18518d4ea6195c44bf00.tar.xz wireguard-linux-f9a2adcc9e908907129c18518d4ea6195c44bf00.zip | |
arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes
Add SCI[0-1] nodes to r9a07g044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211109123110.8543-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions