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| author |   Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-11-06 18:56:23 +0800 |
|---|---|---|
| committer |   Marc Kleine-Budde <mkl@pengutronix.de> | 2020-11-20 12:05:14 +0100 |
| commit | 07b6b3e23cbd531977535b4d1bbef741d13af264 (patch) | |
| tree | 1d9a923e6d8ea5dc406a324b79210c095bfcd9f1 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | dt-bindings: can: fsl,flexcan: add uint32 reference to clock-frequency property (diff) | |
| download | wireguard-linux-07b6b3e23cbd531977535b4d1bbef741d13af264.tar.xz wireguard-linux-07b6b3e23cbd531977535b4d1bbef741d13af264.zip | |
dt-bindings: can: fsl,flexcan: fix fsl,clk-source property
Correct fsl,clk-source example since flexcan driver uses "of_property_read_u8"
to get this property.
Fixes: 9d733992772d ("dt-bindings: can: flexcan: add PE clock source property to device tree")
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Link: https://lore.kernel.org/r/20201106105627.31061-2-qiangqing.zhang@nxp.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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